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Parallel Full Search Algorithm for Motion Estimation on Graphic Processing Unit

[ Vol. 12 , Issue. 4 ]

Author(s):

Fatma Ezzahra Sayadi*, Marwa Chouchene, Haithem Bahri, Randa Khemiri and Mohamed Atri   Pages 317 - 323 ( 7 )

Abstract:


Background: Advances in video compression technology have been driven by everincreasing processing power available in software and hardware.

Methods: The emerging High-Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate.

Results: Thus, the results show high computational complexity. In both standards, the motion estimation block presents a significant challenge in clock latency since it consumes more than 40% of the total encoding time. For these reasons, we proposed an optimized implementation of this algorithm on a low-cost NVIDIA GPU developed with CUDA language.

Conclusion: This optimized implementation can provide high-performance video encoder where the speed reaches about 85.

Keywords:

Compute Unified Device Architecture (CUDA), full Search algorithm, GPU, HEVC, motion estimation, Nvidia optimization method.

Affiliation:

Laboratory of Electronics and Microelectronics EµE, Faculty of Sciences, Monastir University, Monastir, Laboratory of Electronics and Microelectronics EµE, Faculty of Sciences, Monastir University, Monastir, Laboratory of Electronics and Microelectronics EµE, Faculty of Sciences, Monastir University, Monastir, Laboratory of Electronics and Microelectronics EµE, Faculty of Sciences, Monastir University, Monastir, Laboratory of Electronics and Microelectronics EµE, Faculty of Sciences, Monastir University, Monastir

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